Performance Analysis of CMOS Circuits using Shielded Channel Dual Gate Stack Silicon on Nothing Junctionless Transistor

In this paper it has been demonstrated that a shielded channel made by varying the side gate length in silicon-on-nothing junctionless transistor not only improves short effect but also improve performance of CMOS circuits device. The proposed device dual stack silicon on nothing (SCDGSSONJLT) drain induced barrier lowering (DIBL), cut-off frequency and subthreshold slope are improved 20%, 39% 20% respectively over single material insulator (SMG SOI JLT). inverter fall time Tf (pS) noise margin 50% 10% compare to (SCSOIJLT). It observed circuit simulation inverter, NAND NOR static power dissipation case SCDGSSONJLT reduced 45%, 81% 83% SMGSOIJLT. Thus, significant improvement DIBL, frequency, propagation delay at low supply voltage shows is more suitable for circuits.